Forming a doped source and a drain to a semiconductor nanowire presents several challenges. First, it is difficult to in-situ dope nanowires during their growth since dopants are incorporated into the nanowire body from the gas-phase or by radial growth (E. Tutuc et al., Nano Lett, September 2006, in press). For example, a lightly doped portion of a nanowire will be counter-doped if a following segment is grown to be heavily doped. Second, due to growth incubation time the onset for a doped region in in-situ doped nanowires will exhibit variations corresponding to the delay in nucleation each nanowire experienced (B. Kalache et al., JJAP, 45, p. L190, 2006). Third, heavy in-situ doping was shown to lead to nanowire tapering (in Ge nanowires) and loss of gold from the catalyst (in Si nanowires doped with diborane). Fourth, even if segmented doping along a nanowire body can be achieved, there are no simple methods to align the contacts and the gate to each segment. Fifth, dopant variations will make it hard to control doping in thin nanowires. For example, a nanowire segment with a diameter of 10 nm, a length of 0.25 micron and with a doping level of 1E19 cm−3 contains about 200 atoms of the dopant. If the nanowire diameter is reduced to 5 nm, the 0.25 micron segment will contain only about 50 dopant atoms.
To build a metal oxide semiconductor field effect transistor (MOSFET), the nanowire should have an n-p-n (n-FET) or a p-n-p (p-FET) doping profile along the nanowire main axis. Several approaches were proposed to achieve that profile. The first is by in-situ doping of the nanowire during growth (Y. Wang et al., Device Research Conference digest, p. 175, 2006). The disadvantages and limitation of the in-situ technique were discussed earlier. The second approach is based on ion implantation (W. Riess et al., Inter. Conf. on Nanoscience and Technology, Luzern, August 2006). This approach has the disadvantage that it can only be used with fat nanowires (diameters larger than 30 nm) since nanowires with small diameters will be amorphized and sputtered by the implant. Recrystallization of the doped regions may not be possible due to the one-dimensional nature of the nanowire (spontaneous recrystallization will dominate during solid phase epitaxy). As a result, most of the nanowire FETs that were reported to date were fabricated with Schottky (metal) source and drain.
In view of the foregoing, there is a need for providing a nanowire FET with doped semiconductor source and drain regions. To reduce device variability, there is also a need for fabrication methods that do not relay on pre-doped nanowires, but rather use undoped nanowires.